Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
With increasing dual data rate (DDR) speeds and native burst lengths, dynamic random access memory (DRAM) technology today offers very high throughput capabilities to the system. However, along with a high potential throughput gain, the overhead associated with a random access to DRAM data may dramatically increase a cycle count. For example, while sequentially executing memory access commands, different pages in the DRAM may need to be opened to accommodate each sequential memory access command. In an example, a page in the DRAM is opened while executing a memory access command, wherein the page was previously opened (and subsequently closed) while executing another memory access command in the immediate past. This may translate into lower efficiency of the system and longer latencies. Conventional attempts to compensate for these efficiency and latency concerns include the use of faster and more expensive DRAM components.